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[Linux driver] ram2

Description: 双口RAM驱动,此文档是有说明的哦，希望对大家有帮助-Dual-port RAM drive
Platform: | Size: 2048 | Author: he | Hits:

[VHDL-FPGA-Verilog] idt723641

Description: VERILOG双端口驱动IDT的双扣RAM很好用的-VERILOG Twill the IDT dual-port RAM drive good use
Platform: | Size: 14336 | Author: hehh | Hits:

[Linux driver] dualram

Description: 双口RAM驱动程序，对于基于ARM 板子的嵌入式linux开发者，使用到双口RAM，可以在此驱动源码上修改成自己需要的。-Dual-port RAM driver board for ARM-based embedded linux developer, using the dual-port RAM, you can modify the source code in this drive into their needs.
Platform: | Size: 7168 | Author: alex | Hits:

[VHDL-FPGA-Verilog] IPRAM

Description: FPGA内置RAM,调用tools里面的IP核，生成一个双口的RAM，用来存储数据。然后可以用SignalTAP II查看波形或者数据。-FPGA built-in RAM, which is called IP core tools to generate a dual port RAM, used to store data. You can then view the waveform or use SignalTAP II data.
Platform: | Size: 1982464 | Author: xiexin | Hits:

[VHDL-FPGA-Verilog] PCI9054

Description: PCI总线芯片PCI9054本地总线的FPGA控制逻辑。 硬件架构为PCI9054+双口RAM+FPGA。 使用USERo清中断。 该逻辑以在项目中应用。-PCI bus FPGA chip PCI9054 local bus control logic. Hardware architecture PCI9054+ dual-port RAM+ FPGA. Use USERo clear interrupts. The logic to apply in the project.
Platform: | Size: 1024 | Author: 61408520 | Hits:

[VHDL-FPGA-Verilog] SDRAMping-pong-memory-structure

Description: 双口RAM 的乒乓存储结构（芯片型号CY7C09279） 应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging has verified]
Platform: | Size: 1024 | Author: 61408520 | Hits:

[Other] shuangkouRAM

Description: verilog语言，调用FPGA内部配置的双口RAM，并控制采集-verilog language, calling FPGA internal configuration of dual-port RAM, and control the collection
Platform: | Size: 3710976 | Author: 章金敏 | Hits:

[Other] Test_2_Port_RAM

Description: Quartus ii双口RAM模块的使用，包括源码、ram时序图以及测试报告-Use Quartus ii dual-port RAM modules, including source code, ram timing diagram and test reports
Platform: | Size: 7946240 | Author: 刘宇 | Hits:

[VHDL-FPGA-Verilog] ADPUARTPDPRAM

Description: ad7606采集信号数据存入双口ram再通过串口发送出去。- ad7606 collected signal data stored in the dual port ram and then sent through the serial port.
Platform: | Size: 6915072 | Author: wangyang | Hits:

[Internet-Network] 635355963606373750

Description: 本文介绍了应用FPGA实现对高速A/D转换芯片的控制电路，介绍了这一控制的设计思想，并提出了通过双口RAM实现FPGA与慢速度的单片机进行双机数据通信处理的解决方案。-　　　Data acquisition is an item of indispensable technology which is essential to the industrial control system. As the increasing need for speed performance of the data collection requirements, FPGA technology came into being. This paper introduces the high-speed A/D converter by using FPGA chip control circuit detailing, discussing the design of the control circuit, at the same time submitting the FPGA through dual-port RAM and slow-speed single-chip dual-computer data communications solutions. FPGA and Single-chip microcomputer mutual coordination work, control the data acquisition system, and Single-chip microcomputer with rich peripherals can be extended accordingly. The circuit of the design that use VHDL language to complete. Through the program designing and testing, the voltage information which is showed in the PC through serial port transmission collected ultimately. It is successful to realize the mutual communication between FPGA and single-chip microcomputer.
Platform: | Size: 117760 | Author: 陈建华 | Hits:

[Graph program] dpram1_24_240

Description: 24X240 dual port ram
Platform: | Size: 2048 | Author: hojin | Hits:

[Wavelet] dpram1_24_1920

Description: 24x1920 dual port ram
Platform: | Size: 2048 | Author: hojin | Hits:

[VHDL-FPGA-Verilog] cell_arch

Description: cell architecture for dual port ram
Platform: | Size: 1024 | Author: Anish Goel | Hits:

[File Format] ug_ram_rom

Description: This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP cores to implement the memory modes—the ALTSYNCRAM and ALTDPRAM IP cores. The Quartus® II software automatically selects one of these IP cores to implement memory modes. The selection depends on the target device, memory modes, and features of the RAM and ROM.-This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP cores to implement the memory modes—the ALTSYNCRAM and ALTDPRAM IP cores. The Quartus® II software automatically selects one of these IP cores to implement memory modes. The selection depends on the target device, memory modes, and features of the RAM and ROM.
Platform: | Size: 593920 | Author: nacer1606 | Hits:

[VHDL-FPGA-Verilog] Dual-port-RAM-data-acquisition

Description: 利用传统方法设计的高速数据采集系统由于集成度低、电路复杂，高速运行电路干扰大，电路可靠性低，难以满足高速数据采集工作的要求。应用FPGA可以把数据采集电路中的数据缓存、控制时序逻辑、地址译码、总线接口等电路全部集成进一片芯片中，高集成性增强了系统的稳定性，为高速数据采集提供了理想的解决方案。-Using traditional methods of high-speed data acquisition system design due to low integration, circuit complexity, high-speed operation of the circuit interference, low circuit reliability, it is difficult to meet the requirements of high-speed data acquisition work. FPGA application can collect data in the data buffer circuit, control the timing logic, address decoding, bus interface circuit all integrated into a single chip, the high integration enhances the stability of the system, providing the ideal solution for high-speed data acquisition program.
Platform: | Size: 99328 | Author: wu | Hits:

[VHDL-FPGA-Verilog] uart_ram

Description: 串口接收数据校样后存入双口ram,接收完整帧数据后，置中断，通知串口发送-After receiving proof serial data stored in dual port ram, receive a complete frame of data after the interrupt, serial port to send notifications
Platform: | Size: 4377600 | Author: yxs | Hits:

[Software Engineering] HPI-Communication-Design

Description: 介绍了TMS320VC5402的HPI主机接口原理,以一个简单的通信程序作为例子,详细说明通过HPI 口实现5402芯片内部的16 kB 双端口RAM与AT 89 C51单片机的通信过程. -Introduces the principle of TMS320VC5402 HPI host interface, a simple communication program as an example, a detailed description of the chip to achieve by 5402 the HPI port and dual-port RAM 16 kB AT 89 C51 microcontroller communication process.
Platform: | Size: 45056 | Author: 高远 | Hits:

[Other] Example-b4-1

Description: 1.定制一个双端口RAM，DualPortRAM 2.在顶层工程中实例化这个RAM 3.实现这个工程，在Quartus II仿真器中做门级仿真 在ModelSim中对这个工程进行RTL级仿真-1. Customize a dual-port RAM, DualPortRAM 2. In the top-level project instantiate RAM 3. To achieve this project, do gate-level simulator in Quartus II Simulation In this works in ModelSim RTL-level simulation
Platform: | Size: 319488 | Author: 朱潮勇 | Hits:

[VHDL-FPGA-Verilog] Dual_ram_verilog_CODE

Description: 写了FIFO中要用到的双口RAM的模块,FIFO中的RAM只用于读数据,输出数据,用写时针采集信号,读时针那一端不用读时针来采样.-Written to use the FIFO dual port RAM module, FIFO in the RAM is only used to read data, output data, the clock signal acquisition with write and read without reading that end of the hour to hour sampling.
Platform: | Size: 1024 | Author: dagegegoni | Hits:

[Linux driver] IDT7026

Description: 双口RAM驱动程序及测试，具体设计时可参考，采用sem实现-Dual-port RAM and test driver
Platform: | Size: 13312 | Author: Zivery | Hits:
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